Memory device controllers, such as PCI SSD controllers, generally operate in two different controller environments. The first environment is a host-based environment in which flash translation logic (FTL) resides in the host software driver and the controller hardware performs hardware functions. The second environment is an embedded processor environment in which the FTL resides in embedded CPUs on the controller.
As such, these controller environments sometimes require the use of standardized protocols to communicate memory device commands, such as NVMe or SCSI over PCle (SOP). These controller environments may also be implemented in a manner that requires vendor-specific protocols (i.e., non-NVME or non-SOP protocols). As such, the software and hardware structures included in these controller environments must be properly configured in order to support these different types of protocols. Accordingly, many conventional memory device controller systems are often unable to process memory device commands in a manner that efficiently accounts for these differences.
Furthermore, conventional approaches often fail to efficiently schedule the processing of memory device commands. For instance, conventional approaches are often unable to account for any interdependencies related to the processing of memory device commands or handle the inherent temporal ordering of such commands in a coherent fashion.